| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a delay fixed loop capable of increasing an operating frequency of a DRAM, even when a frequency of an input clock increases, by securing operating margin which allows generation of a rising/polling out enable signal R/FOUTEN using a second DLL clock FCLK_DLLOE. <P>SOLUTION: An output driver comprises a first driving section for receiving a clock output from the delayed fixed loop; generating a first DLL clock for use in outputting of read data, and driving with a first timing delay; and a second driving section for receiving the clock output from the delay fixed loop, generating a second DLL clock for use in reducing current consumption during a write operation, and driving with a second timing delay which is smaller than the first timing delay. <P>COPYRIGHT: (C)2007,JPO&INPIT |
