Delay circuit for electronic device testing apparatus, generates desired time delay by changing junction capacitance of FET through which shaped signal passes

摘要

The source and drain of a FET are connected to a path through which the shaped signal transmits. The shaped signal is delayed by a desired time by controlling a capacitance between source and drain, by applying desired voltage to the gate electrode. Independent claims are also included for the following: (a) Testing apparatus; (b) A capacitor.