发明名称 |
TRI-STATING A PHASE LOCKED LOOP TO CONSERVE POWER |
摘要 |
In a system with an intermittently operating radio, the frequency of which is controlled by a Phase Locked Loop (PLL), a method and system for reducing the power consumed by the PLL by tri-stating the control capacitor in the PLL after the PLL has stabilized at a design frequency. After the capacitor is stabilized, power to some of the components in the PLL is reduced.
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申请公布号 |
US2007082635(A1) |
申请公布日期 |
2007.04.12 |
申请号 |
US20060467346 |
申请日期 |
2006.08.25 |
申请人 |
CYPRESS SEMICONDUCTOR CORP. |
发明人 |
GEHRING MARK R.;MOYAL NATHAN |
分类号 |
H04B1/18;H04B1/06;H04B7/00 |
主分类号 |
H04B1/18 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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