发明名称 |
Low Noise Vertical Variable Gate Control Voltage JFET Device in a BiCMOS Process and Methods to Build this Device |
摘要 |
We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a channel region over the buried layer contacting gate regions that connect to a gate terminal. The channel region, of which the length spans the distance between the buried layer and a source region, is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.
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申请公布号 |
US2007080400(A1) |
申请公布日期 |
2007.04.12 |
申请号 |
US20060609551 |
申请日期 |
2006.12.12 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
PENDHARKER SAMEER P.;HAO PINGHAI;WU XIAOJU |
分类号 |
H01L29/76;H01L21/337;H01L21/8249;H01L27/06;H01L29/10;H01L29/808 |
主分类号 |
H01L29/76 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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