发明名称 |
SEMICONDUCTOR HETEROSTRUCTURE AND FORMING METHOD OF SEMICONDUCTOR HETEROSTRUCTURE |
摘要 |
<P>PROBLEM TO BE SOLVED: To provide a method of forming heterostructure, and a corresponding semiconductor heterostructure having a better surface roughness and/or embedding border plane roughness property. <P>SOLUTION: A method of forming the semiconductor heterostructure, comprising the steps of: offering a substrate having a first inplane lattice parameter a<SB>1</SB>; preparing a buffer layer having a second inplane lattice parameter a<SB>2</SB>; and preparing an upper portion layer on this buffer layer, is characterized in that an additional layer is prepared between the buffer layer and upper portion layer for improving the surface roughness of the semiconductor heterostructure, and in that this additional layer has a third inplane lattice parameter a<SB>3</SB>locating between the first and second lattice parameters. <P>COPYRIGHT: (C)2007,JPO&INPIT |
申请公布号 |
JP2007096274(A) |
申请公布日期 |
2007.04.12 |
申请号 |
JP20060218649 |
申请日期 |
2006.08.10 |
申请人 |
SOI TEC SILICON ON INSULATOR TECHNOLOGIES SA |
发明人 |
KENARD MARK;FIGUET CHRISTOPHE |
分类号 |
H01L21/205;C23C16/24;C23C16/28;C23C16/42;H01L21/02;H01L21/762;H01L27/12;H01L33/00 |
主分类号 |
H01L21/205 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|