| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a receiver having a function of precisely measuring a delay time and a gain while an increase in circuit scale is suppressed. <P>SOLUTION: In reception mode, a received signal is processed by a reception processing circuit part 2. An FPGA 9 of this reception processing circuit 2 generates a reference signal Ref of a PLL circuit 10 generating a local signal Lc of a mixer 5, and a test signal Tt of the RF band is generated by a frequency multiplexer 13 and a mixer 14 based upon the reference signal and supplied to the reception processing circuit 2 in test mode. A leading edge of the test signal Tt processed by the reception processing circuit part 2 is detected by the FPGA 9 and recorded in a memory 12 to measure the delay time of the receiver 1 from the number of addresses needed up to the recording of it. Further, the gain of the receiver 1 is detected from amplitudes of the test signal Tt processed by the reception processing circuit part 2 and a test signal Tt processed by a long amplifier 17. <P>COPYRIGHT: (C)2007,JPO&INPIT |
