发明名称 SIGNAL HOLDING CIRCUIT, DRIVER CIRCUIT, ELECTROCHEMICAL DEVICE AND ELECTRONIC APPARATUS
摘要 PROBLEM TO BE SOLVED: To accurately hold the level of an analog signal at all times without a refresh operation. SOLUTION: A signal holding circuit 1A has first and second voltage followers B1 and B2. A first switch S1 is connected electrically between an input terminal IN and the input end of the first voltage follower B1. The first switch S1 is brought to an on state for a writing period while being brought to an off state for a holding period. A second switch S2 is connected between the output end of the second voltage follower B2 and the input end of the first voltage follower B1. The second switch S2 is brought to the off-state for the writing period while being brought to the on state for the holding period. A feedback loop is constituted for the holding period, and an input voltage signal Vin is held. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007096594(A) 申请公布日期 2007.04.12
申请号 JP20050281516 申请日期 2005.09.28
申请人 SEIKO EPSON CORP 发明人 KASAI TOSHIYUKI
分类号 H03K17/00 主分类号 H03K17/00
代理机构 代理人
主权项
地址