| 摘要 |
PROBLEM TO BE SOLVED: To obtain a semiconductor integrated circuit having a micro-cell structure reducing a cell area without deteriorating performance characteristics. SOLUTION: An n well region 2 is formed at the center of a p well region 1. N active regions 4a and 4b are formed to an upper section and a lower section in a plan view of the n well region 2. P-well contact regions 5a and 5b are extended and formed in the horizontal direction to the upper section and the lower section in the plan view of the n active region 4a in the p well region 1. A p active region 3 is formed at a center in the n well region 2. An n well contact region 6 is formed while being extended to in the vertical direction to the left side of the p active region 3. A well contact section 14c as a part of a metallic wiring layer 14 for a VDD crossing at the center of the p active region 3 is formed on the n well contact region 6, and the well contact section 14c and the n well contact region 6 are connected electrically through a plurality of contact holes 21. COPYRIGHT: (C)2007,JPO&INPIT
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