发明名称 |
A METHOD OF FORMING A GATE STACK CONTAINING A GATE DIELECTRIC LAYER HAVING REDUCED METAL CONTENT |
摘要 |
<p>A method is provided for reducing the metal content and controlling the metal depth profile of a gate dielectric layer in a gate stack. The method includes providing a substrate in a process chamber, depositing a gate dielectric layer on the substrate, where the gate dielectric layer includes a metal element. The metal element is selectively etched from at least a portion of the gate dielectric layer to form an etched gate dielectric layer with reduced metal content, and a gate electrode layer is formed on the etched gate dielectric layer.</p> |
申请公布号 |
WO2007041040(A2) |
申请公布日期 |
2007.04.12 |
申请号 |
WO2006US37079 |
申请日期 |
2006.09.22 |
申请人 |
TOKYO ELECTRON LIMITED;O'MEARA, DAVID, L.;LEE, YOUNGJONG;WAJDA, CORY |
发明人 |
O'MEARA, DAVID, L.;LEE, YOUNGJONG;WAJDA, CORY |
分类号 |
H01L31/119;H01L27/108;H01L21/8242;H01L29/76;H01L29/94 |
主分类号 |
H01L31/119 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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