发明名称 CLOCK DRIVER CONTROL CIRCUIT OF DELAY FIXED LOOP
摘要 <P>PROBLEM TO BE SOLVED: To provide a DLL device for reducing an operating current for a DRAM by preventing that a DLL clock is meaninglessly toggled and ringed to sections other than a necessary section where the clock is actually used, not only in a power down mode or a self refresh mode but also in a normal mode operation. <P>SOLUTION: The DLL driver control circuit includes the DLL driver for driving the DLL clock and a DLL driver controller for generating a control signal to control the driving of the DLL driver in response to a signal having information associated with an active mode. <P>COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007095267(A) 申请公布日期 2007.04.12
申请号 JP20060182746 申请日期 2006.06.30
申请人 HYNIX SEMICONDUCTOR INC 发明人 KIM KYUNG-HOON
分类号 G11C11/407;G06F1/04;H03L7/08;H03L7/081 主分类号 G11C11/407
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