发明名称 |
Fast buffer pointer across clock |
摘要 |
<p>Retiming circuitry for retiming a data signal transmitted from a first environment under control of a first clock signal to a second environment under control of a second clock signal, said first and second clock signals having a known repeat relationship, the retiming circuitry comprising a plurality of delay elements for delaying said data signal; a plurality of inputs connected to said delay elements for receiving said data signal at respectfully different delays; selection means for selecting the data signal at one of said inputs based on said known repeat relationship; and an output for outputting said selected data signal.</p> |
申请公布号 |
EP1772795(A1) |
申请公布日期 |
2007.04.11 |
申请号 |
EP20050256294 |
申请日期 |
2005.10.10 |
申请人 |
STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED |
发明人 |
ELLIOTT, PAUL;BENNETT, PETER |
分类号 |
G06F1/12 |
主分类号 |
G06F1/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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