| 摘要 |
A decoding LSI adaptable to MPEG4 is provided with a padding means for performing padding on decoded texture data, an arithmetic decoding means for performing arithmetic decoding on coded shape data, and a composition means for compositing a plurality of texture data to generate composite image data. The padding means, the arithmetic decoding means, and the composition means are implemented by hardware circuits, i.e., a padding engine, an arithmetic decoding engine, and a composition engine, respectively. Therefore, the decoding LSI can perform high-speed decoding on a bitstream corresponding to plural objects, such as images, which are compressively coded by the MPEG4 coding method, with reduced cost of the hardware circuits performing the decoding process. |
