发明名称 |
Test systems and methods with compensation techniques |
摘要 |
The present invention relates to test systems for testing integrated circuit devices and to calibration associated systems and methods. One embodiment of the invention provides a method for providing formatted levels for use in a test system. The method includes: providing on a single CMOS IC, a timing generation circuit operative to provide timing information signals; and a formatter in communication with the timing generation circuit.
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申请公布号 |
US7203875(B2) |
申请公布日期 |
2007.04.10 |
申请号 |
US20040841019 |
申请日期 |
2004.05.07 |
申请人 |
CREDENCE SYSTEMS CORPORATION |
发明人 |
SYED AHMED RASHID |
分类号 |
G01R31/317;G01R31/28;G01R31/319;G01R31/333;G11C29/00;G11C29/56 |
主分类号 |
G01R31/317 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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