发明名称 Apparatus and method for low latency power management on a serial data link
摘要 An apparatus and method for low latency power management on a serial data link are described. In one embodiment, the method includes the detection of an electrical idle exit condition during receiver operation in an electrical idle state. Once detected, data synchronization is performed according to one or more received data synchronization training patterns. Finally, when the synchronization is performed within a determined synchronization re-establishment period, the receiver will resume operation according to a normal power state. Accordingly, the embodiment described illustrates an open loop, low latency power resumption operation for power management within 3GIO links.
申请公布号 US7203853(B2) 申请公布日期 2007.04.10
申请号 US20020302295 申请日期 2002.11.22
申请人 INTEL CORPORATION 发明人 MARTWICK ANDREW W.;DROTTAR KEN;DUNNING DAVID S.;SCHOENBORN ZALE T.;VOLK ANDREW M.;SWARTZ RONALD W.;MILLER DENNIS J.
分类号 G06F12/00;G06F1/32 主分类号 G06F12/00
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