发明名称 SCALABLE PARALLEL PIPELINE FLOATING-POINT UNIT FOR VECTOR PROCESSING
摘要 <p>An embodiment of the present invention is a technique to perform floating-point operations for vector processing. An input queue captures a plurality of vector inputs. A scheduler dispatches the vector inputs. A plurality of floating-point (FP) pipelines generates FP results from operating on scalar components of the vector inputs dispatched from the scheduler. An arbiter and assembly unit arbitrates use of output section and assembles the FP results to write to the output section.</p>
申请公布号 WO2007038576(A1) 申请公布日期 2007.04.05
申请号 WO2006US37635 申请日期 2006.09.26
申请人 INTEL CORPORATION;DONOFRIO, DAVID;DWYER, MICHAEL 发明人 DONOFRIO, DAVID;DWYER, MICHAEL
分类号 G06F15/78;G06F9/38 主分类号 G06F15/78
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