发明名称 A LOW LATENCY MESSAGE PASSING MECHANISM PRIORITY INFORMATION
摘要 <p>In one embodiment, a method is provided. The method of this embodiment provides detecting by a network controller a flush occurring on a host bus of a DM ("direct messaging") packet to a memory from a first cache line associated with a first processor; obtaining and storing the DM packet at a second cache line associated with the network controller; and sending the DM packet over a network to a third cache line associated with a second processor.</p>
申请公布号 WO2007038574(A1) 申请公布日期 2007.04.05
申请号 WO2006US37633 申请日期 2006.09.26
申请人 INTEL CORPORATION;CHITLUR, NAGABHUSHAN;RANKIN, LINDA;DUNNING, DAVE;LIAO, MICHAEL;GUPTA, MARUTI 发明人 CHITLUR, NAGABHUSHAN;RANKIN, LINDA;DUNNING, DAVE;LIAO, MICHAEL;GUPTA, MARUTI
分类号 G06F13/38;G06F12/08 主分类号 G06F13/38
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