| 摘要 |
An exemplary state monitoring circuit includes a data transform unit, a counter, and a clock generator. The data transform unit is connected to a system management bus (SMBUS) to obtain serial signals output from the SMBUS, and convert the serial signals to parallel signals. The counter is connected to a south bridge chip of the system and the data transform unit, for counting parallel signals converted by the data transform unit, if the count is finished, the counter sends a reset signal to the south bridge chip. The clock generator is connected to the counter for providing a clock frequency signal to the counter.
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