| 摘要 |
<P>PROBLEM TO BE SOLVED: To greatly lower costs by reducing the chip area of a driving LSI. <P>SOLUTION: This display system previously stores correction data on which display unevenness of each pixel is reflected in a fast serial I/F flash memory 40A and reads the correction data out of the fast serial I/F flash memory 40A at high speed, and a composition circuit 42A in the driving LSI 50A puts the correction data together with externally input image data in real time to generate corrected display data Vsig which are output to an organic EL display panel 300. The driving LSI 50A operates with a master clock MCLK, but reading of the correction data from the fast serial I/F flash memory 40A is performed on the basis of a serial clock SCK synchronized with the master clock MCLK. <P>COPYRIGHT: (C)2007,JPO&INPIT |
