| 摘要 |
A design tool, which is capable of designing an IC in which no malfunctions occur during a normal operation and a test, by limiting the amount of noise produced by the operation of an SRAM during the normal operation of the IC itself and during the test of the IC, has been disclosed. The design tool is for a semiconductor device having plural SRAMs in one chip, comprising a simultaneous operation noise amount calculation section for estimating AC noise produced by the simultaneous operation of the SRAMs and performing design such that the estimated AC noise is less than the permitted amount of noise.
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