发明名称 Power-up implementation for block-alterable memory with zero-second erase time
摘要 A block-alterable memory, e.g., a flash memory, having substantially zero erase time is coupled to host. The block-alterable memory includes a controller that reads block information from the memory on power up to determine if a block of the memory is usable. The controller updates block map latches only if the block is usable. The controller also updates block status latches according to the block information. Thus, information about each block of the memory is easily accessible in the latches when the block alterable memory becomes ready for use on power up.
申请公布号 US2007079055(A1) 申请公布日期 2007.04.05
申请号 US20050240840 申请日期 2005.09.30
申请人 CHANDRAMOULI SUBRAMANYAM;BABB EDWARD M;LI BO 发明人 CHANDRAMOULI SUBRAMANYAM;BABB EDWARD M.;LI BO
分类号 G06F12/00 主分类号 G06F12/00
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