| 摘要 |
In order to provide an error detection / correction circuit (100; 100') as well as a method for detecting and/or for correcting at least one error of at least one data word, said data word comprising - information in the form of at least one information bit or at least one pay load data bit, and - redundancy in the form of at least one check bit or at least one redundant bit, wherein the number of the one or more check bits or redundant bits being supplemented to the respective data word is optimized, in particular wherein at least one physical memory space can be used in an optimized way depending on the requirements of the application, it is proposed - to perform at least one first error correction scheme being assigned to at least one first data path (30; 30'), and - to perform at least one second error correction scheme -- being assigned to at least one second data path (40; 40'), and -- being designed for increasing the information and/or the redundancy, in particular --- for increasing the number of the one or more information bits or of the one or more pay load data bits and/or --- for increasing the number of the one or more check bits or of the one or more redundant bits, of the respective data word being transmitted through the second data path (40; 40'). |
