A hardware memory architecture or arrangement is proposed, suited for multi-processor systems or arrays. The invention is to add between a functional unit (computation unit) and at least one memory device, which said functional unit accesses (for write and/or read), at least one memory queue.
申请公布号
WO2007003370(A3)
申请公布日期
2007.04.05
申请号
WO2006EP06375
申请日期
2006.06.30
申请人
INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW;SAMSUNG ELECTRONICS CO., LTD.;MEI, BINGFENG;KIM, SUK, JIN;ALLAM, OSMAN