| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide an on-screen display circuit capable of prescribing a timing of data input or data output with reference to an edge of an input clock even when a frequency of an external input clock is high. <P>SOLUTION: First to Nth intermediate clocks S131-S132 are generated by dividing delay factors from a dot clock input terminal 101 to an internal operation clock 108. An input timing of a synchronization signal S105 input to a synchronization signal input terminal 102 is adjusted to match an internal operation clock S106 by first to Nth input timing adjustment flip-flops 122-124 operating at the first to Nth intermediate clocks or the dot clock S104. An output timing of the signal S106 output from a display output terminal 103 is adjusted to match the dot clock S104 by the first to Nth output timing adjustment flip-flops 128-130 operated at the first to Nth intermediate clocks or the dot clock S104. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
