| 摘要 |
PROBLEM TO BE SOLVED: To obtain a synchronous memory device being suitable for a bus system minimizing clock-data skew. SOLUTION: The bus system minimizing clock-data skew includes a clock line segment for transmitting clock and a clock line segment for receiving clock, these segments are joined to each other by a turnaround at one end, one or a plurality of synchronous memory devices can be joined to such bus system. The synchronous memory system is constituted so that writing data proceed simultaneously in the same direction as the receiving clock and reading data proceed simultaneously in the same direction as the transmitting clock, also, data bits of the writing data and the reading data are received and transmitted conforming to dual edge transfer in which transfer is performed with a frequency being two times of the receiving clock and the transmitting clock. COPYRIGHT: (C)2007,JPO&INPIT
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