发明名称 |
Memory and driving method of the same |
摘要 |
According to the invention, mounting area is decreased and yield is improved by decreasing the number of elements, and a memory with less burden on peripheral circuitry and a driving method thereof are provided. The invention comprises a memory cell including a memory element in a region where a bit line and a word line cross with an insulator interposed between them, a column decoder, and a selector including a clocked inverter. An input node of the clocked inverter is connected to the bit line while an output node is connected to a data line. Among a plurality of transistors connected in series which form the clocked inverter, a gate of a P-type transistor of which source or drain is connected to a power source on the high potential side VDD and a gate of an N-type transistor of which source or drain is connected to a power source on the low potential side VSS are connected to the column decoder.
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申请公布号 |
US2007076515(A1) |
申请公布日期 |
2007.04.05 |
申请号 |
US20060607053 |
申请日期 |
2006.12.01 |
申请人 |
SEMICONDUCTOR ENERGY LABORATORY CO., LTD. |
发明人 |
SHIONOIRI YUTAKA;ATSUMI TOMOAKI;KATO KIYOSHI |
分类号 |
G11C8/00;G11C17/18;G11C7/10;G11C7/12;G11C11/4094;G11C11/418;G11C11/419;G11C17/08;G11C17/12;H03K17/00;H03K17/687;H03K17/693 |
主分类号 |
G11C8/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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