发明名称 METHOD FOR FORMING PLATING FILM FOR WIRING BOARD
摘要 PROBLEM TO BE SOLVED: To form a wiring layer or a via in which the generation of voids in a plating layer is suppressed when copper electroplating is performed to a trench or a via hole with a high aspect ratio formed at an insulating layer. SOLUTION: A film containing an additive accelerating electroplating is selectively formed on the bottom face part of a trench or a via hole, and then, copper electroplating is performed. The plating acceleration additive-containing film at the bottom face part is formed by performing aeration as an opening board for plating formation is dipped into a plating acceleration additive-containing solution, so as to remove bubbles in the opening part, and thereafter performing a spin rinsing process and drying treatment. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007084891(A) 申请公布日期 2007.04.05
申请号 JP20050276870 申请日期 2005.09.22
申请人 FUJITSU LTD 发明人 MIYAHARA SHOICHI;KARASAWA KAZUAKI;FUKUDA HIROYUKI
分类号 C25D7/12;H01L21/28;H01L21/288;H01L21/3205;H01L23/52 主分类号 C25D7/12
代理机构 代理人
主权项
地址