发明名称 |
PHASE LOCKED LOOP AND METHOD FOR ADJUSTING THE FREQUENCY AND PHASE IN THE PHASE LOCKED LOOP |
摘要 |
A phase locked loop (PLL) which includes a phase frequency detector coupled with a time to digital converter capable of comparing a reference signal with an oscillator signal and generating a digital value representing the phase difference between the reference signal and the oscillator signal. The PLL further includes a state machine for phase acquisition that is capable of generating a control value depending on the digital value, and a controllable oscillator that is capable of generating the oscillator signal depending on the control value.
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申请公布号 |
US2007075785(A1) |
申请公布日期 |
2007.04.05 |
申请号 |
US20060469423 |
申请日期 |
2006.08.31 |
申请人 |
KOSSEL MARCEL A;MORF THOMAS E;SCHMATZ MARTIN L;WEHRLI SILVAN |
发明人 |
KOSSEL MARCEL A.;MORF THOMAS E.;SCHMATZ MARTIN L.;WEHRLI SILVAN |
分类号 |
H03L7/00 |
主分类号 |
H03L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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