| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide an output control signal generation circuit in which clock transfer is unnecessary and the latch margin of a first latch circuit does not depend on the period of an external clock. <P>SOLUTION: The output control signal generation circuit is provided with latch circuit groups 100 to 109 connected in cascade and a timing signal generation circuit TC for generating timing signals to be supplied to the latch circuit groups 100 to 109 on the basis of a second clock whose phase is advanced from that of a first clock used for taking in a read command. The timing signal generation circuit TC delays the phase of a timing signal to be supplied to a relatively prestage latch circuit from a timing signal to be supplied to a relatively post-stage latch circuit included in the latch circuit groups 100 to 109. Since the latch margin of the first latch circuit 100 does not depend on the period of the external clock, correct control can be performed even when the clock is in an extremely high-speed state. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
