发明名称 Dynamic random access memory system with bank conflict avoidance feature
摘要 A memory system having multiple memory banks is configured to prevent bank conflict between access requests. The memory system includes a memory controller and a plurality of memory banks operatively coupled to the memory controller, with each of the memory banks configured for storing a plurality of data items. More particularly, a given data item is stored as multiple copies of the data item with a given one of the multiple copies in each of a designated minimum number of the memory banks. The memory controller is adapted to process requests for access to the data items stored in the memory banks in accordance with a specified bank access sequence. The minimum number of memory banks for storage of the multiple copies of the given data item may be determined as a function of a random cycle time and a random bank access delay of the memory banks, e.g., as an integer greater than or equal to a ratio of the random cycle time to the random bank access delay. The memory system is preferably operable in the above-described bank conflict avoidance mode as well as a standard random access mode. The memory system is particularly well-suited for use in an application involving an unbalanced ratio of read and write accesses, e.g., as an external tree memory for a network processor integrated circuit, but can also be used in numerous other processing device memory applications.
申请公布号 EP1345125(A3) 申请公布日期 2007.04.04
申请号 EP20020258105 申请日期 2002.11.25
申请人 AGERE SYSTEMS INC. 发明人 BOUCHARD, GREGG A.;CALLE, MAURICIO;RAMASWAMI, RAVI
分类号 G06F12/06;G06F13/16;G11C7/00 主分类号 G06F12/06
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