| 摘要 |
The method involves depositing a sacrificial gate layer whose thickness defines length of vertical monocrystalline semiconductor channels (36). A semiconductor material of a drain region is epitaxially grown in layer's vertical holes to form the channels and a source region (38). The layer is removed while subsisting the channels between the regions in a cavity. An insulating sheath (46) is formed around each channel. The cavity is filled by a conductive material of a definitive gate (50). Interconnections (56) are formed in contact with a drain contact region (17), region (38) and gate. An independent claim is also included for a vertical field effect transistor. |
