| 摘要 |
A semiconductor device, such as a vertical DMOS device, has a gate (10), a source and a drain, an n-type body region (1) a p-type well region (2) a highly doped n-type region (6) in the well region, the well region being adjacent to the body region to form a neck in the body region. The neck has a localized increase in dopant concentration having a local maximum at a depth (4) away from an upper surface of the body. This can help to reduce ON resistance and provide a high breakdown voltage, provided it is at a similar depth as a depth (3) of a maximum dopant concentration of the well region. If the dopant concentration at the upper surface of the body is unaffected by the localized increase, then CMOS devices can be integrated in the same well region. |
