| 摘要 |
In the present invention, an apparatus and method for performing alpha blending calculations in a fast and efficient manner is disclosed. When implemented as an integrated circuit, the apparatus of the present invention occupies reduced area. The apparatus comprises a plurality of multiplexers and an adder. Each of multiplexers is configured to receive a bit value, alpha<SUB>i</SUB>, of the digital value alpha, alpha. Each of the plurality of multiplexers is configured to receive the first and second digital image values. Each of the plurality of multiplexers is also configured to direct to outputs of the multiplexers either the first or second digital image value responsive to the bit value, alpha<SUB>i</SUB>. Each of the outputs of the plurality of multiplexers is shifted left according to the order of the bit values, alpha<SUB>i</SUB>, to produce a plurality of left-shifted outputs. The adder is produces the sum of the left-shifted outputs.
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