发明名称 High speed I-O loopback testing with low speed DC test capability
摘要 A loopback circuit for testing low and high frequency operation of integrated circuit transmitter and receiver components. First and second resistors forming a first branch of the circuit are series-connected between first and second circuit ports. Third and fourth resistors forming a second branch of the circuit are series-connected between third and fourth circuit ports. A DC isolator is connected between the first and second branches. At lower frequencies, the two branches are DC-isolated, enabling ATE-measurement of the transmitter's output drive level independently of the receiver, continuity testing of ESD protection structures, etc. At higher frequencies, the transmitter's output signal is split into three portions, each of which is attenuated by a selected amount. One of the attenuated signal portions is applied to the receiver to test the receiver's sensitivity, independently of possible excess resiliency in the transmitter's output drive level.
申请公布号 US7200170(B1) 申请公布日期 2007.04.03
申请号 US20020193131 申请日期 2002.07.12
申请人 PMC-SIERRA, INC. 发明人 DESANDOLI LISA ANN;HISSEN JURGEN;FERGUSON KENNETH WILLIAM;BIRK GERSHOM
分类号 H04B3/46 主分类号 H04B3/46
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