发明名称 Logic circuit arrangement
摘要 A logic circuit arrangement including at least two data signal inputs, at which at least two data signals are provided, a first signal path coupled to the data signal inputs, and having a plurality of transistors of a first conduction type, and a plurality of control inputs coupled to the transistors.
申请公布号 US7199618(B2) 申请公布日期 2007.04.03
申请号 US20040996620 申请日期 2004.11.19
申请人 INFINEON TECHNOLOGIES AG 发明人 GLIESE JOERG;SCHEPPLER MICHAEL
分类号 H03K19/096;H03K19/173 主分类号 H03K19/096
代理机构 代理人
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