发明名称 |
Method of operating a memory at high speed using a cycle ready status output signal |
摘要 |
A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.
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申请公布号 |
US7200730(B2) |
申请公布日期 |
2007.04.03 |
申请号 |
US20030663144 |
申请日期 |
2003.09.16 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
SHEFFIELD BRYAN D.;AGRAWAL VIKAS K.;SPRIGGS STEPHEN W.;BADI ERIC L. |
分类号 |
G06F13/00;G11C7/10;G11C7/22 |
主分类号 |
G06F13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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