发明名称 DECODER AND DECODING METHOD
摘要 PROBLEM TO BE SOLVED: To restrain deterioration in the decoding performance of an LDPC code, and to miniaturize a decoder. SOLUTION: A quasi-check node calculator 412 performs a check node arithmetic operation of a check node for decoding the LDPC code, and one portion of a variable node arithmetic operation of a variable node for decoding the LDPC code as a quasi-check node arithmetic operation. A quasi-variable node calculator 415 performs another portion of the variable node arithmetic operation as quasi-variable node arithmetic operation. In integration performed by the quasi-variable node arithmetic operation, an integral result is outputted which is expressed by the quantization value of the number of bits that is larger than that to be integrated by 1 bit. The quasi-check node calculator 412 can be applied to, for example, a decoder, or the like that is built in a tuner for receiving satellite broadcasting for decoding the LDPC code. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007081602(A) 申请公布日期 2007.03.29
申请号 JP20050264731 申请日期 2005.09.13
申请人 SONY CORP 发明人 YOKOGAWA MINESHI;SHINTANI OSAMU
分类号 H03M13/19;G06F11/10;H04L1/00 主分类号 H03M13/19
代理机构 代理人
主权项
地址