发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To enable a failure portion to be specified in a single degenerate failure event, using a simple circuit configuration in a scan chain test of a semiconductor integrated circuit that has been scan designed. SOLUTION: In each of two or more flip-flops Fi (i=1, 2, ...) connected to each other as a scan chain, between combinational circuits C1, C2 functioning as preceding and latter stages, and each having a scan data input terminal DT other than a data input terminal D, a reverse feedback input line, having an inverter Ini, is connected to an output line; and a selector Si is disposed to select either a scan-in terminal Sin, the output line of the preceding stage flip-flop Fi-1 or the reverse feedback input line of the own stage flip-flop Fi, and to connect it to the scan data input terminal DT of the flip-flop Fi. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007078441(A) 申请公布日期 2007.03.29
申请号 JP20050264690 申请日期 2005.09.13
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 NISHI KIYOKAZU
分类号 G01R31/28;H01L21/822;H01L27/04 主分类号 G01R31/28
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