发明名称 Methods of forming integrated circuit devices having metal interconnect structures therein
摘要 Methods of forming metal interconnect structures include forming a first electrically insulating layer on a semiconductor substrate and forming a second electrically insulating layer on the first electrically insulating layer. The second and first electrically insulating layers are selectively etched in sequence to define a contact hole therein. A first metal layer (e.g., tungsten) is deposited. This first metal layer extends on the second electrically insulating layer and into the contact hole. The first metal layer is then patterned to expose the second electrically insulating layer. The second electrically insulating layer is selectively etched for a sufficient duration to expose the first electrically insulating layer and expose a metal plug within the contact hole. This selective etching step is performed using the patterned first metal layer as an etching mask. A seam within the exposed metal plug is then filled with an electrically conductive filler material (e.g., CoWP). A second metal layer is then formed on the exposed metal plug containing the electrically conductive filler material.
申请公布号 US2007072406(A1) 申请公布日期 2007.03.29
申请号 US20050237987 申请日期 2005.09.28
申请人 LEE KYOUNG W;KU JA-HUM;HONG DUK H;PARK WAN J 发明人 LEE KYOUNG W.;KU JA-HUM;HONG DUK H.;PARK WAN J.
分类号 H01L21/4763 主分类号 H01L21/4763
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