| 摘要 |
Disclosed is a method of forming a copper interconnection using a dual damascene process, in which an etch profile anomaly and the trench depth variation caused by the trench etching process are reduced or prevented, so that the copper interconnection is obtained substantially without voids or interconnection defects. The method includes the steps of depositing a first dielectric layer, forming an etch stop layer having an etching selectivity with respect to the first dielectric layer, and depositing a second dielectric layer thereon. Since the via holes and the trench are simultaneously formed through the etching process using the etch stop layer, the trench depth may be precisely controlled, the manufacturing processes is simplified and the reliability of the semiconductor device is improved.
|
