| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory controller which detects inconsistency of the access timing to a synchronous memory. SOLUTION: This memory controller has: a request cycle number storage part 42 for storing the cycle number of a clock signal CLK required up to second processing from first processing; a detecting part 43 for detecting the first and second processing in access to an SDRAM 2; a counting part 44 for counting the cycle number of the clock signal CLK up to detecting the second processing after detecting the first processing by the detecting part 43; a determining part 45 for determining whether the access to the SDRAM 2 is adapted to an access procedure by comparing a counting value of the counting part 44 with the cycle number of the request cycle number storage part 42; and a connecting terminal 71 for informing the occurrence of an error when determining that the access to the SDRAM 2 is not adapted to the access procedure by the determining part 45. COPYRIGHT: (C)2007,JPO&INPIT
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