DUAL-PROCESSOR COMPLEX DOMAIN FLOATING-POINT DSP SYSTEM ON CHIP

摘要

A system for digital signal processing, configured as a system on chip (SoC) (102), combines a microprocessor core (106) and digital signal processor (DSP) core (108) with floating-point data processing capability. The DSP core (108) can perform operations on floating-point data in a complex domain and is capable of producing real and imaginary arithmetic results simultaneously. This capability allows a single-cycle execution of, for example, FFT butterflies, complex domain simultaneous addition and subtraction, complex multiply accumulate (MULACC), and real domain dual multiply-accumulators (MACs). The SoC (102) may be programmed entirely from a microprocessor programming interface (140), using calls from a DSP library to execute DSP functions. The cores (106, 108) may also be programmed separately. Capability for programming and simulating the entire SoC (102) are provided by a seprate programming environment. The SoC (102) may have heterogeneous processing cores in which either processing core may act as master or slave, or both cores may operate simultaneously and independently.