| 摘要 |
<p>Provided is a decoding device for low-density parity inspection codes, which is simplified in constitution and enabled to perform high-speed processing operations neither by using a RAM and nor by needing a complicated control. The decoding device is constituted to comprise a variable-check message generation unit (11), in which a variable-check operator block (32) having an adder (41) is interposed between registers (31) corresponding to one arrangement in a testing matrix, and a check-variable message generation unit (12), in which a check-variable operation block (62) having a comparator is interposed between registers (61) corresponding to one arrangement in the testing matrix.</p> |
