| 摘要 |
A hardware register content retention system ( 100 ) includes a hardware register ( 110 ) configured to store register content and a memory ( 120 ) capable of storing multiple entries per register coupled to the hardware register, configured to receive a dump of the register content from the hardware register in response to initiation of a task interrupt and to restore the register content to the hardware register in response to termination of the task interrupt. The retention system also includes a controller ( 130 ) coupled to the hardware register and the memory, configured to control transfer of the register content between the hardware register and the memory. In one aspect of the invention, the memory is a first-in, first-out (FIFO) queue. The present invention enables more efficient retention of hardware register content than approaches implemented in software. Further, register content may be saved in parallel thereby increasing the speed of register content retention. |
