| 摘要 |
A delayed locked loop, capable of a duty cycle compensation, resets if a phase difference between outputs from delay blocks in the delay locked loop is over a predetermined amount after a delay locking state is achieved. The delay locked loop includes a duty cycle compensator for receiving first and second clocks and a reset control block for resetting the delay locked loop if a phase difference between the first and second clocks is over a predetermined amount after the delay locked loop achieves a delay locking state.
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