| 摘要 |
A semiconductor for performing DMA without using a FIFO unit includes a memory for storing data, a CPU for processing data, a universal asynchronous receiver/transmitter (UART) and a control circuit block. The control circuit block controls storage of receive data, which is output from the UART, in the memory based on an upper address output from the CPU and a lower address output from the UART in the DMA mode and controls storage of transmit data, which is transmitted by the CPU, in the memory in response to a transfer address generated by the CPU in the CPU access mode. The UART in the DMA mode extracts receive data from a received receive frame and outputs the receive data to the control circuit block, or receives the transmit data read from the memory based on the upper address and the lower address, generates a transmit frame including the transmit data and outputs the transmit frame. In the DMA mode, a clock signal supplied to the CPU is intercepted.
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