发明名称 Packet transfer apparatus having network address translation circuit which enables high-speed address translation during packet reception processing
摘要 In a packet transfer apparatus for transferring packets between first and second networks, a translated network address is assigned to a first node in the first network and having a first private network address when the first packet from the first node is transferred to a second node in the second network, and said translated network address is stored in an address management circuit associated with said first and second network addresses. Thereafter, address translation for realizing an NAT function is performed on subsequent packets transferred between the first and second nodes, by a dedicated hardware circuit and reference to the address management circuit, while performing processing for receiving the packets.
申请公布号 US7197035(B2) 申请公布日期 2007.03.27
申请号 US20020102796 申请日期 2002.03.22
申请人 FUJITSU LIMITED 发明人 ASANO KAZUYA
分类号 H04L12/56;H04L12/28;H04L12/46;H04L29/06;H04L29/08;H04L29/12 主分类号 H04L12/56
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