发明名称 |
Method for setting design margin for LSI |
摘要 |
After predicting a relationship between a design margin set against a fabrication variation in design of an LSI and a yield, a specific design margin for attaining a given yield is calculated based on the predicated relationship. The yield is a delay yield obtained by cumulating a signal propagation delay time thereby achieving a probability that a signal propagated through a logic circuit of the LSI is delayed by a given amount of time, and the design margin is a derating factor indicating a ratio between the signal propagation delay time and a standard value of the signal propagation delay time.
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申请公布号 |
US7197728(B2) |
申请公布日期 |
2007.03.27 |
申请号 |
US20040868832 |
申请日期 |
2004.06.17 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
YONEZAWA HIROKAZU |
分类号 |
G06F17/50;H01L21/82;H01L29/00 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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