发明名称 Electrostatic-protection dummy transistor structure
摘要 A semiconductor apparatus where output and protection transistors are different in transistor structure, and where, even when breakdown in the output transistor occurs earlier than in the protection transistor, an ESD surge current does not concentrate in the output transistor inferior in ESD resistance. Formed in its output circuit, where the drain and source of a first-conductivity-type, e.g. NMOS, output transistor 11 are connected respectively to an output electrode and to ground, is an NMOS protection transistor 10 of which the drain and source are connected respectively to the drain and source of the NMOS output transistor 11 and of which the gate is directly connected to a second-conductivity-type layer, a P-well 22 , under the gate electrode of the NMOS output transistor 11 . By this means, an electrostatic surge does not concentrate in the NMOS output transistor 11.
申请公布号 US7196378(B2) 申请公布日期 2007.03.27
申请号 US20040810668 申请日期 2004.03.29
申请人 OKI ELECTRIC INDUSRTY CO., LTD. 发明人 ICHIKAWA KENJI
分类号 H01L23/62;H01L27/04;H01L21/822;H01L21/8238;H01L27/01;H01L27/02;H01L27/08;H01L27/092;H01L27/12 主分类号 H01L23/62
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