| 摘要 |
An integrated chip has a clock signal input ( 1.1 ) for application of a first clock signal (clk 1 ) and a clock signal output ( 1.2-1.5 ). Moreover, it has a phase locked loop ( 2 ), which, on the input side, is connected to the clock signal input ( 1.1 ) and serves far generating a second clock signal (clk 2 ). Furthermore, the chip has a multiplexer (MUX), via which the first clock signal (clk 1 ) or the second clock signal (clk 2 ) can optionally be switched to the clock signal output ( 1.2-1.5 ), and a unit for frequency monitoring ( 3 ), which, on the input side, is connected to the clock signal input ( 1.1 ) and is designed and can be operated in such a way that, in the event of a limiting frequency (fmin) being undershot, the multiplexer (MUX) is caused to switch the first clock signal (clk 1 ) to the clock signal output ( 1.2-1.5 ).
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