| 摘要 |
PROBLEM TO BE SOLVED: To effectively conduct a regression test by reducing simulation time during verification of a logic circuit. SOLUTION: A logic circuit verification apparatus includes a registering means for registering a plurality of sets of verification items for the logic circuit; a simulation means for simulating the logic circuit about the verification items; a plurality of monitoring means allocated to the plurality of respective sets for monitoring the operation of the logic circuit corresponding to the verification items during the simulation; a holding means for holding the verification items about which the operation is checked through the monitoring; and a control means which, if all the verification items included in the sets are held in the holding means, stops the operation of the monitoring means allocated to the sets. COPYRIGHT: (C)2007,JPO&INPIT
|
